FIG. 1 is a block diagram illustrating an example of a conventional segment DAC. This segment DAC is comprised of any number of segments, and the same number of D-type flip-flops (DFF). Each of the segments included in the DAC receives a 1-bit signal from the Q output and Q* (* means inversion) output of a DFF from the digital part. According to that 1-bit signal, each segment outputs a signal of “+1” or “−1” in the form of a differential signal (positive output and negative output). The positive output and negative output that constitute each differential output obtained from these segments are added to each other by being connected to a positive output line and a negative output line, respectively. An analog output is obtained as a result.
FIG. 2 shows the output waveform of one segment in the segment DAC having the aforementioned configuration. The upper part in FIG. 2 shows the ideal waveform, while the lower part in FIG. 2 shows the actual output waveform. As shown in the upper part in FIG. 2, it is ideal for the output of the segment DAC that the value changes instantaneously without accompanying the transient response. In the actual circuit, however, it is difficult to realize that characteristic. As shown in the lower part in FIG. 2, in the DAC output, the output value varies in conjunction with the transient response. In the case of the actual circuit, if the rising transient response when the value changes from “−1” to “+1” and the falling transient response when the value changes from “+1” to “−1” are completely consistent with each other, the performance of the DAC will not be affected. In the actual circuit, however, the influence of the circuit configuration of each segment and mismatches of the circuit elements used causes differences to occur between the rising transient response characteristic and the falling transient response characteristic, and such differences will aggravate the distortion of the DAC. Consequently, when such a configuration is adopted, a proper circuit design is required in order to reduce the mismatching that causes the differences in the transient response of each segment.
In one of the conventional circuit design methods for reducing such mismatching, the areas of transistors, resistors, or other circuit elements included in each said segment are increased to reduce the dimensional error of each circuit element. When using this method, however, a very large circuit area is required to realize each segment. Also, the area of the IC chip used for the DAC will be increased.
Another circuit technology for reducing mismatching uses a correcting current source for example, Japanese Kokai Patent Application No. 2000-332610. In this method, a correcting current source is adopted in a current adding type D/A converter in order to reduce the secondary distortion caused by the difference between the rising and falling rates of the converter output voltage. The correcting current source supplies a correcting current temporarily in order to speed up the slow rising rate. A circuit used to detect the change point of the digital input value is also adopted in order to control supply of the correcting current from the correcting current source. Consequently, in this method, in order to generate a highly-accurate output, it is necessary to use accurate circuits such as the correcting current source and the change point detecting circuit in order to increase the accuracy. As a result, the circuit configuration becomes complicated, and the circuit area is increased.
The aforementioned transient response error also occurs in many other electrical circuits or circuit devices besides the DAC.